Realization of a SDR DBF for Micro-Satellite SAR on FPGA

On bi-static or multi-static space-borne radar the appropriate digital beam-former (DBF) algorithms can obtain multi-angular synthetic aperture radar (SAR) data and enhance signal-tonoise ratio. Some applications ask for short revisit time that need to ensure seamless coverage to obtain a wide swath SAR image data with a single satellite using digital beam-forming on receive scheme [1]. The transmitter and receiver antennas of the bi-static SAR for the micro-satellite can be mounted on a single carrier or placed on separate platforms [2]. Due to the reasons that the crosstrack errors [3] of the distributed micro-satellite constellation and satellite fading channel errors will result in the phase difference among the received signals of each array antenna element, the proposed software defined radio (SDR) DBF is designed with the configuration of two antennas on a same micro-satellite. For the purpose of simplifying the phase compensation among the received signals from the array antenna elements and reducing the downlink transmission load, the proposed SDR DBF is to be realized on the board processor of micro-satellite. For micro-satellite SAR systems [4], power consumption is an important issue. The reconfigurable feature of the SDR architecture gives rise to reusability of hardware, scalability, and power efficiency [5]. Reusability of hardware supporting multiple modes of DBF strives for compactness and efficient power consumption. In this paper, according to the SDR architecture, a DBF system comprising multiplebeams, direction of arrival (DOA) estimation and null steering beam modes is realized using an field programmable gate array (FPGA) for the micro-satellite SAR system. In multiple-beam mode, the beam steering function is performed with high resolution. In DOA mode, the direction of the undesired interference signal is estimated using SAR receiver processing. In null steering beam mode, the receiver end on SAR can resist the interference to improve its anti-jamming capability. The mode could be chosen with software upgrading to achieve the hardware reconfiguration of the processing modules according to the variety of operation requirements.